Method for programming antifuse-type one time programmable memory cell

ABSTRACT

A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse transistor. A first bit line voltage is transmitted to the antifuse transistor. A first voltage stress with a first polarity is provided to a gate oxide layer of the antifuse transistor to form a weak path between the gate terminal and the first drain/source terminal of the antifuse transistor. Secondly, a second program voltage is provided to the gate terminal of the antifuse transistor. A second bit line voltage is transmitted to the antifuse transistor. A second voltage stress with a second polarity is provided to the gate oxide layer of the antifuse transistor. Consequently, a program current is generated along the weak path to rupture the gate oxide layer above the first drain/source terminal.

This application claims the benefit of U.S. provisional application Ser.No. 62/280,137, filed Jan. 19, 2016, the disclosure of which isincorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present invention relates to a method for programming a non-volatilememory cell, and more particularly to a method for programming anantifuse-type one time programmable memory cell.

BACKGROUND OF THE INVENTION

As is well known, a non-volatile memory is able to continuously retaindata after the supplied power is interrupted. Generally, after thenon-volatile memory leaves the factory, the user may program thenon-volatile memory in order to record data into the non-volatilememory.

According to the number of times the non-volatile memory is programmed,the non-volatile memories may be classified into a multi-timeprogrammable memory (also referred as a MTP memory), a one timeprogrammable memory (also referred as an OTP memory) and a mask readonly memory (also referred as a Mask ROM).

Generally, the MTP memory can be programmed many times, and the storeddata of the MTP memory can be modified many times. On the contrary, theOTP memory can be programmed once. After the OTP memory is programmed,the stored data cannot be modified. Moreover, after the Mask ROM leavesthe factory, all stored data have been recorded therein. The user isonly able to read the stored data from the Mask ROM, but is unable toprogram the Mask ROM.

Moreover, depending on the characteristics, the OTP memories may beclassified into two types, i.e. a fuse-type OTP memory and anantifuse-type OTP memory. Before a memory cell of the fuse-type OTPmemory is programmed, the memory cell has a low-resistance storagestate. After the memory cell of the fuse-type OTP memory is programmed,the memory cell has a high-resistance storage state.

On the other hand, the memory cell of the antifuse-type OTP memory hasthe high-resistance storage state before programmed, and the memory cellof the antifuse-type OTP memory has the low-resistance storage stateafter programmed.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a method for programmingan antifuse-type one time programmable memory cell. The antifuse-typeone time programmable memory cell includes a first control transistorand a first antifuse transistor. The first control transistor includes agate terminal, a first drain/source terminal and a second drain/sourceterminal. The first antifuse transistor includes a gate terminal and afirst drain/source terminal. The first drain/source terminal of thefirst antifuse transistor is connected with the second drain/sourceterminal of the first control transistor. The method includes thefollowing steps. In a step (a), a first program voltage is provided tothe gate terminal of the first antifuse transistor, and the firstcontrol transistor is turned on. A first bit line voltage is transmittedfrom the first drain/source terminal of the first control transistor tothe first drain/source terminal of the first antifuse transistor. Afirst voltage stress with a first polarity is provided to a gate oxidelayer of the first antifuse transistor. A weak path is formed betweenthe gate terminal of the first antifuse transistor and the firstdrain/source terminal of the first antifuse transistor. In a step (b), asecond program voltage is provided to the gate terminal of the firstantifuse transistor, and the first control transistor is turned on. Asecond bit line voltage is transmitted from the first drain/sourceterminal of the first control transistor to the first drain/sourceterminal of the first antifuse transistor. A second voltage stress witha second polarity is provided to the gate oxide layer of the firstantifuse transistor. A program current is generated along the weak path.Consequently, the gate oxide layer of the first antifuse transistor isruptured.

Numerous objects, features and advantages of the present invention willbe readily apparent upon a reading of the following detailed descriptionof embodiments of the present invention when taken in conjunction withthe accompanying drawings. However, the drawings employed herein are forthe purpose of descriptions and should not be regarded as limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will becomemore readily apparent to those ordinarily skilled in the art afterreviewing the following detailed description and accompanying drawings,in which:

FIG. 1A is a schematic cross-sectional view of an antifuse-type one timeprogrammable memory cell according to an embodiment of the presentinvention;

FIG. 1B is a schematic equivalent circuit diagram of the antifuse-typeone time programmable memory cell according to the embodiment of thepresent invention;

FIGS. 2A-2D schematically illustrate associated voltage signals forprogramming and reading the OTP memory cell according to the embodimentof the present invention;

FIGS. 3A-3C schematically illustrate different ruptured positions of thegate oxide layer of the antifuse transistor;

FIG. 3D is a plot illustrating the relationship between the number ofOTP memory cells in the first storing state and the read current;

FIG. 4A schematically illustrates associated voltage signals forprogramming the OTP memory cell to the first storing state in the firststage of the program cycle;

FIG. 4B schematically illustrates associated voltage signals forprogramming the OTP memory cell to the first storing state in the secondstage of the program cycle;

FIG. 4C is a plot illustrating the relationship between the number ofOTP memory cells in the first storing state and the read current, inwhich the program cycle is divided into two stages;

FIG. 5 is a schematic equivalent circuit diagram of a memory array withthe OTP memory cells of the present invention;

FIG. 6A schematically illustrates associated voltage signals forprogramming the OTP memory cell of the memory array of FIG. 5 to thefirst storing state in the first stage of the program cycle;

FIG. 6B schematically illustrates associated voltage signals forprogramming the OTP memory cell of the memory array of FIG. 5 to thefirst storing state in the second stage of the program cycle;

FIG. 7A is a schematic equivalent circuit diagram of an antifuse-typeone time programmable memory cell according to another embodiment of thepresent invention;

FIG. 7B schematically illustrates associated voltage signals forprogramming the OTP memory cell FIG. 7A to the first storing state inthe first stage of the program cycle;

FIG. 7C schematically illustrates associated voltage signals forprogramming the OTP memory cell FIG. 7A to the first storing state inthe second stage of the program cycle;

FIG. 8A is a schematic equivalent circuit diagram of an antifuse-typeone time programmable memory cell according to a further embodiment ofthe present invention;

FIG. 8B schematically illustrates associated voltage signals forprogramming the OTP memory cell FIG. 8A to the first storing state inthe first stage of the program cycle;

FIG. 8C schematically illustrates associated voltage signals forprogramming the OTP memory cell FIG. 8A to the first storing state inthe second stage of the program cycle; and

FIG. 9 is a schematic circuit diagram illustrating a variant example ofthe OTP memory cell of FIG. 8A.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1A is a schematic cross-sectional view of an antifuse-type one timeprogrammable memory cell according to an embodiment of the presentinvention. FIG. 1B is a schematic equivalent circuit diagram of theantifuse-type one time programmable memory cell according to theembodiment of the present invention. For brevity, the antifuse-type onetime programmable memory cell is also referred as an OTP memory cell.

As shown in FIG. 1A, the OTP memory cell 10 is constructed in a P-wellregion PW. A first doped region 11, a second doped region 12 and a thirddoped region 13 are formed under a top surface of the P-well region PW.The first doped region 11 is connected with a bit line BL.

A first gate structure 16 is formed on the top surface of the P-wellregion PW and disposed over the region between the first doped region 11and the second doped region 12. A second gate structure 19 is formed onthe top surface of the P-well region PW and disposed over the regionbetween the second doped region 12 and the third doped region 13. Thefirst gate structure 16 comprises a first gate oxide layer 14 and afirst gate 15. The first gate 15 is connected with a word line WL. Thesecond gate structure 19 comprises a second gate oxide layer 17 and asecond gate 18. The second gate 18 is connected with an antifuse controlline AF.

The first doped region 11, the second doped region 12 and the first gatestructure 16 are collaboratively formed as a control transistor Tc. Thesecond doped region 12, the third doped region 13 and the second gatestructure 19 are collaboratively formed as an antifuse transistor Taf.

Please refer to FIG. 1B. A first drain/source terminal of the controltransistor Tc is connected with the bit line BL. A gate terminal of thecontrol transistor Tc is connected with the word line WL. A firstdrain/source terminal of the antifuse transistor Taf is connected with asecond drain/source terminal of the control transistor Tc. A gateterminal of the antifuse transistor Taf is connected with the antifusecontrol line AF.

FIGS. 2A-2D schematically illustrate associated voltage signals forprogramming and reading the OTP memory cell according to the embodimentof the present invention.

Please refer to FIG. 2A. For programming the OTP memory cell to a firststoring state, a ground voltage (e.g., 0V) is provided to the bit lineBL, a control voltage Vdd is provided to the word line WL, and a programvoltage Vp is provided to the antifuse control line AF. In anembodiment, the magnitude of the control voltage Vdd is in the rangebetween 0.75V and 3.6V, and the program voltage Vp is in the rangebetween 4V and 11V.

Since the control voltage Vdd is provided to the word line WL and theground voltage (e.g., 0V) is provided to the bit line BL, the controltransistor Tc is turned on. Meanwhile, the ground voltage (e.g., 0V) istransmitted to the antifuse transistor Taf through the controltransistor Tc. In addition, the voltage stress of the program voltage Vpis applied to the gate oxide layer of the antifuse transistor Taf. Sincethe program voltage Vp is beyond the withstanding voltage range of theantifuse transistor Taf, a program current Ip is outputted from theantifuse transistor Taf. The program current Ip flows to the bit line BLthrough the control transistor Tc.

Moreover, due to the program current Ip, the gate oxide layer of theantifuse transistor Taf is ruptured. The ruptured gate oxide layer maybe considered as a resistor with a low resistance value. In other words,the antifuse transistor Taf connected with the control transistor Tc isconsidered as a low-resistance resistor. Under this circumstance, theOTP memory cell 10 is in the first storing state.

Please refer to FIG. 2B. For programming the OTP memory cell 10 to asecond storing state, the control voltage Vdd is provided to the bitline BL, the control voltage Vdd is provided to the word line WL, andthe program voltage Vp is provided to the antifuse control line AF.

Since the control voltage Vdd is provided to the word line WL and thebit line BL, the control transistor Tc is turned off. Since the controltransistor Tc is turned off, the gate oxide layer of the antifusetransistor Taf is not ruptured. The gate oxide layer that is notruptured may be considered as a resistor with a high resistance value ofseveral mega ohms.

Since the gate oxide layer is not ruptured, the OTP memory cell 10 doesnot generate the program current. In other words, the antifusetransistor Taf connected with the control transistor Tc is considered asa high-resistance resistor. Under this circumstance, the OTP memory cell10 is in the second storing state.

During the read cycle, the ground voltage (e.g., 0V) is provided to thebit line BL, the control voltage Vdd is provided to the word line WL,and a read voltage Vread is provided to the antifuse control line AF.According to the magnitude of a read current flowing through the bitline BL, the OTP memory cell 10 is verified to have the first storingstate or the second state. In an embodiment, the magnitude of the readvoltage Vread is in the range between 0.75V and 3.6V.

Please refer to FIG. 2C. In this situation, the OTP memory cell 10 is inthe first storing state. When the control transistor Tc is turned on inresponse to the control voltage Vdd, the antifuse transistor Tafgenerates a read current Ir in response to the read voltage Vread. Theread current Ir flows to the bit line BL through the control transistorTc, and the magnitude of the read current Ir is several microamperes(μA).

Please refer to FIG. 2D. In this situation, the OTP memory cell 10 is inthe second storing state. When the control transistor Tc is turned on inresponse to the control voltage Vdd, the antifuse transistor Tafgenerates a read current Ir in response to the read voltage Vread. Themagnitude of the read current Ir flowing through the bit line BL isnearly zero (or much lower than 1 μA).

In other words, during the read cycle, the OTP memory cell 10 is judgedto have the first storing state or the second storing state according tothe magnitude of the read current flowing through the bit line BL.

However, due to the process variation, some problems occur. For example,when the voltage stress of the program voltage Vp is applied to the gateoxide layer of the antifuse transistor Taf, the ruptured position of thegate oxide layer is somewhat different. Consequently, the magnitude ofthe read current Ir is different.

FIGS. 3A-3C schematically illustrate different ruptured positions of thegate oxide layer of the antifuse transistor.

Please refer to FIG. 3A. After the program action is completed, theruptured position of the gate oxide layer is located between the gateterminal of the antifuse transistor Taf and the first drain/sourceterminal of the antifuse transistor Taf. Under this circumstance, theresistor between the gate terminal of the antifuse transistor Taf andthe first drain/source terminal of the antifuse transistor Taf has thelowest resistance. Consequently, the read current Ir has the largestcurrent value during the read cycle.

Due to the process variation, the ruptured position of the gate oxidelayer as shown in FIG. 3B and the ruptured position of the gate oxidelayer as shown in FIG. 3C are possible. As shown in FIG. 3B, theruptured position of the gate oxide layer is located between the gateterminal of the antifuse transistor Taf and the channel of the antifusetransistor Taf. As shown in FIG. 3C, the ruptured position of the gateoxide layer is located between the gate terminal of the antifusetransistor Taf and the second drain/source terminal of the antifusetransistor Taf.

In case that the situation of FIG. 3B or the situation of FIG. 3Coccurs, the resistor between the gate terminal of the antifusetransistor Taf and the first drain/source terminal of the antifusetransistor Taf has a higher resistance. Consequently, the read currentIr has the smaller current value during the read cycle. If the readcurrent Ir is too small, the OTP memory cell is possibly misjudged asthe second storing state.

FIG. 3D is a plot illustrating the relationship between the number ofOTP memory cells in the first storing state and the read current. Afterthe OTP memory cells are programmed to the first storing state, a smallamount of OTP memory cells still have smaller read currents. Forexample, the read current Ir of the OTP memory cells circumscribed bythe dotted frame I is smaller than 5 μA. These OTP memory cell ispossibly misjudged as the second storing state.

As mentioned above, the read current Ir of the OTP memory cellscircumscribed by the dotted frame I is very low. That reason may be thatthe ruptured position of the gate oxide layer of the antifuse transistorTaf is not optimal during the program cycle.

For solving the above drawbacks, the present invention provides a novelmethod for programming the OTP memory cell. During the program cycle,the OTP memory cell is programmed to the first storing state in twostages. In the first stage of the program cycle, a voltage stress with afirst polarity is provided to the region between the gate terminal ofthe antifuse transistor Taf and the first drain/source terminal of theantifuse transistor Taf. Consequently, a weak path is formed between thegate terminal of the antifuse transistor Taf and the first drain/sourceterminal of the antifuse transistor Taf. In other words, under the abovebias condition of the first stage, there will be a localized oxidedamage region generated in the gate oxide layer of the antifuse Taf toform the weak path. In addition, a weak current in a first direction isgenerated in the weak path. The weak current in the first directionflows from the first drain/source terminal of the antifuse transistorTaf to the gate terminal of the antifuse transistor Taf.

In the second stage of the program cycle, a voltage stress with a secondpolarity is provided to the region across the gate oxide layer of theantifuse transistor Taf. Consequently, a program current in a seconddirection is generated. Because of the pre-established weak path duringthe first stage of the program cycle, the program current in the seconddirection flows along the weak path, and flows from the gate terminal ofthe antifuse transistor Taf to the first drain/source terminal of theantifuse transistor Taf. Consequently, the gate oxide layer of theantifuse transistor Taf is ruptured.

After the two stages of the program cycle are completed, the OTP memorycell is programmed to the first storing state. Moreover, it is confirmedthat the ruptured position of the gate oxide layer is located betweenthe gate terminal of the antifuse transistor Taf and the firstdrain/source terminal of the antifuse transistor Taf.

FIG. 4A schematically illustrates associated voltage signals forprogramming the OTP memory cell to the first storing state in the firststage of the program cycle. For example, the nominal voltage of theantifuse transistor Taf is 1.5V. In the first stage of the programcycle, a bit line voltage Vb1 is provided to the bit line BL, a controlvoltage Vdd is provided to the word line WL, and a program voltage Vp1is provided to the antifuse control line AF. In an embodiment, thecontrol voltage Vdd is 3V, the bit line voltage Vb1 is 2V, and theprogram voltage Vp1 is 0V. That is, the bit line voltage Vb1 is higherthan the program voltage Vp1.

Since the control transistor Tc is turned on, the bit line voltage Vb1(2V) is transmitted from the first drain/source terminal of the controltransistor Tc to the first drain/source terminal of the antifusetransistor Taf through the control transistor Tc. Consequently, thevoltage at the gate terminal of the antifuse transistor Taf is lowerthan the voltage at the first drain/source terminal of the antifusetransistor Taf. Meanwhile, the antifuse transistor Taf is turned off,and thus the channel cannot be formed. Under this circumstance, avoltage stress with the negative polarity (−2V) is provided to theregion between the gate terminal of the antifuse transistor Taf and thefirst drain/source terminal of the antifuse transistor Taf.

Since the voltage stress with the negative polarity (−2V) is slightlybeyond the nominal voltage of the antifuse transistor Taf (e.g., 1.5V),the gate oxide layer of the antifuse transistor Taf is not ruptured.However, because of a band-to-band hot hole injection effect and a weakedge tunneling effect, the weak path is formed between the gate terminalof the antifuse transistor Taf and the first drain/source terminal ofthe antifuse transistor Taf. In addition, the weak current iw in thefirst direction flows through the weak path. The weak current iw in thefirst direction flows from the first drain/source terminal of theantifuse transistor Taf to the gate terminal of the antifuse transistorTaf.

FIG. 4B schematically illustrates associated voltage signals forprogramming the OTP memory cell to the first storing state in the secondstage of the program cycle. In the second stage of the program cycle, abit line voltage Vb2 is provided to the bit line BL, the control voltageVdd is provided to the word line WL, and a program voltage Vp2 isprovided to the antifuse control line AF. In an embodiment, the bit linevoltage Vb2 is 0V, and the program voltage Vp2 is 8V. That is, theprogram voltage Vp2 is higher than the bit line voltage Vb1, and the bitline voltage Vb1 is higher than the bit line voltage Vb2.

Since the control transistor Tc is turned on, the bit line voltage Vb2(e.g., 0V) is transmitted from the first drain/source terminal of thecontrol transistor Tc to the first drain/source terminal of the antifusetransistor Taf through the control transistor Tc. Consequently, thevoltage at the gate terminal of the antifuse transistor Taf is higherthan the voltage at the first drain/source terminal of the antifusetransistor Taf. Under this circumstance, a voltage stress with thepositive polarity (+8V) is provided to the region across the gate oxidelayer of the antifuse transistor Taf.

Since the voltage stress with the positive polarity (+8V) is largelybeyond the withstanding voltage of the antifuse transistor Taf, aprogram current Ip with the higher magnitude is generated. The programcurrent Ip flows along the pre-established weak path. Consequently, thegate oxide layer of the antifuse transistor Taf is ruptured. Moreover,the program current Ip flows in a second direction. That is, the programcurrent Ip flows from the gate terminal of the antifuse transistor Tafto the first drain/source terminal of the antifuse transistor Taf.

After the two stages of the program cycle are completed, the OTP memorycell is programmed to the first storing state. Moreover, it is confirmedthat the ruptured position of the gate oxide layer is arranged betweenthe gate terminal of the antifuse transistor Taf and the firstdrain/source terminal of the antifuse transistor Taf.

FIG. 4C is a plot illustrating the relationship between the number ofOTP memory cells in the first storing state and the read current, inwhich the program cycle is divided into two stages. After plural OTPmemory cells are programmed to the first storing state, the readcurrents Ir for almost all of OTP memory cells are not smaller than 5μA. Consequently, the possibility of misjudging the storing states ofOTP memory cells is largely reduced.

FIG. 5 is a schematic equivalent circuit diagram of a memory array withthe OTP memory cells of the present invention. As shown in FIG. 5, thememory array comprises OTP memory cells c11˜c24 in a 2×4 array. Each OTPmemory cell comprises a control transistor Tc and an antifuse transistorTaf. The OTP memory cells c11˜c14 in the first row are connected with abit line BL1. The OTP memory cells c21˜c24 in the second row areconnected with a bit line BL2. The OTP memory cells c11 and c21 areconnected with a word line WL1 and an antifuse control line AF1. The OTPmemory cells c12 and c22 are connected with a word line WL2 and anantifuse control line AF2. The OTP memory cells c13 and c23 areconnected with a word line WL3 and an antifuse control line AF3. The OTPmemory cells c14 and c24 are connected with a word line WL4 and anantifuse control line AF4.

Take the OTP memory cell c13 as an example. A method of programming theOTP memory cell c13 to the first storing state will be described asfollows.

For programming the OTP memory cell c13, the bit line BL1 is a selectedbit line, the word line WL3 is a selected word line, and the antifusecontrol line AF3 is a selected antifuse control line.

FIG. 6A schematically illustrates associated voltage signals forprogramming the OTP memory cell of the memory array of FIG. 5 to thefirst storing state in the first stage of the program cycle. During thefirst stage of the program cycle, the bit line voltage Vb1 (e.g., 2V) isprovided to the bit line BL1, the control voltage Vdd (e.g., 3V) isprovided to the word line WL3, and the program voltage Vp1 (e.g., 0V) isprovided to the antifuse control line AF3. Moreover, the bit linevoltage Vb2 (e.g., 0V) is provided to the non-selected bit line BL2, anoff voltage (e.g., 0V) is provided to the non-selected word lines WL1,WL2 and WL4, and the program voltage Vp1 (e.g., 0V) is provided to thenon-selected antifuse control lines AF1, AF2 and AF4.

Under this circumstance, a voltage stress with the negative polarity(−2V) is provided to the region between the gate terminal and the firstdrain/source terminal of the antifuse transistor Taf of the OTP memorycell c13. Moreover, a weak path is formed between the gate terminal ofthe antifuse transistor Taf and the first drain/source terminal of theantifuse transistor Taf. In other words, under the above bias conditionof the first stage, there will be a localized oxide damage regiongenerated in the gate oxide layer of the antifuse Taf to form the weakpath. In addition, a weak current iw in the first direction flows fromthe first drain/source terminal of the antifuse transistor Taf to thegate terminal of the antifuse transistor Taf.

FIG. 6B schematically illustrates associated voltage signals forprogramming the OTP memory cell of the memory array of FIG. 5 to thefirst storing state in the second stage of the program cycle. During thesecond stage of the program cycle, the bit line voltage Vb2 (e.g., 0V)is provided to the bit line BL1, the control voltage Vdd (e.g., 3V) isprovided to the word line WL3, and the program voltage Vp2 (e.g., 8V) isprovided to the antifuse control line AF3. Moreover, the control voltageVdd (e.g., 3V) is provided to the non-selected bit line BL2, the offvoltage (e.g., 0V) is provided to the non-selected word lines WL1, WL2and WL4, and the program voltage Vp1 (e.g., 0V) is provided to thenon-selected antifuse control lines AF1, AF2 and AF4.

Under this circumstance, a voltage stress with the positive polarity(+8V) is provided to the region across the gate oxide layer of theantifuse transistor Taf of the OTP memory cell c13. Moreover, a programcurrent Ip flows in a second direction is generated by the antifusetransistor Taf. The program current Ip flows along the pre-establishedweak path. That is, the program current Ip flows from the gate terminalof the antifuse transistor Taf to the first drain/source terminal of theantifuse transistor Taf. Consequently, the gate oxide layer of theantifuse transistor Taf is ruptured.

After the two stages of the program cycle are completed, the OTP memorycell is programmed to the first storing state. Moreover, it is confirmedthat the ruptured position of the gate oxide layer is arranged betweenthe gate terminal of the antifuse transistor Taf and the firstdrain/source terminal of the antifuse transistor Taf.

The method of programming the OTP memory cell to the first storing statein two stages can be applied to the other types of OTP memory cells.

FIG. 7A is a schematic equivalent circuit diagram of an antifuse-typeone time programmable memory cell according to another embodiment of thepresent invention. As shown in FIG. 7A, the OTP memory cell 70 comprisesa control transistor Tc1, a control transistor Tc2 and an antifusetransistor Taf. A first drain/source terminal of the control transistorTc1 is connected with a bit line BL. A gate terminal of the controltransistor Tc1 is connected with the word line WL. A first drain/sourceterminal of the control transistor Tc2 is connected with a seconddrain/source terminal of the control transistor Tc1. A gate terminal ofthe control transistor Tc2 is connected with a select line SE. A firstdrain/source terminal of the antifuse transistor Taf is connected with asecond drain/source terminal of the control transistor Tc2. A gateterminal of the antifuse transistor Taf is connected with the antifusecontrol line AF.

FIG. 7B schematically illustrates associated voltage signals forprogramming the OTP memory cell FIG. 7A to the first storing state inthe first stage of the program cycle. In the first stage of the programcycle, a bit line voltage Vb1 is provided to the bit line BL, a controlvoltage Vdd1 is provided to the word line WL, a control voltage Vdd2 isprovided to the select line SE, and a program voltage Vp1 is provided tothe antifuse control line AF. In an embodiment, the control voltage Vdd1is 3V, the control voltage Vdd2 is 3V, the bit line voltage Vb1 is 2V,and the program voltage Vp1 is 0V. The bit line voltage Vb1 is higherthan the program voltage Vp1. The control voltage Vdd2 is higher than orequal to the control voltage Vdd1.

Since the control transistor Tc1 and the control transistor Tc2 areturned on, the bit line voltage Vb1 (2V) is transmitted from the firstdrain/source terminal of the control transistor Tc1 to the firstdrain/source terminal of the antifuse transistor Taf through the controltransistor Tc1 and the control transistor Tc2. Consequently, the voltageat the gate terminal of the antifuse transistor Taf is lower than thevoltage at the first drain/source terminal of the antifuse transistorTaf. Meanwhile, the antifuse transistor Taf is turned off, and thus thechannel cannot be formed. Under this circumstance, a voltage stress withthe negative polarity (−2V) is provided to the region between the gateterminal of the antifuse transistor Taf and the first drain/sourceterminal of the antifuse transistor Taf.

Since the voltage stress with the negative polarity (−2V) is slightlybeyond the nominal voltage of the antifuse transistor Taf (e.g., 1.5V),the gate oxide layer of the antifuse transistor Taf is not ruptured.However, a weak path is formed between the gate terminal of the antifusetransistor Taf and the first drain/source terminal of the antifusetransistor Taf. In other words, under the above bias condition of thefirst stage, there will be a localized oxide damage region generated inthe gate oxide layer of the antifuse Taf to form the weak path. Inaddition, a weak current iw in a first direction flows through the weakpath. The weak current iw flows from the first drain/source terminal ofthe antifuse transistor Taf to the gate terminal of the antifusetransistor Taf.

FIG. 7C schematically illustrates associated voltage signals forprogramming the OTP memory cell FIG. 7A to the first storing state inthe second stage of the program cycle. In the second stage of theprogram cycle, a bit line voltage Vb2 is provided to the bit line BL,the control voltage Vdd1 is provided to the word line WL, the controlvoltage Vdd2 is provided to the select line SE, and a program voltageVp2 is provided to the antifuse control line AF. In an embodiment, thebit line voltage Vb2 is 0V, and the program voltage Vp2 is 8V. That is,the program voltage Vp2 is higher than the bit line voltage Vb1, and thebit line voltage Vb1 is higher than the bit line voltage Vb2.

Since the control transistor Tc1 and the control transistor Tc2 areturned on, the bit line voltage Vb2 (e.g., 0V) is transmitted from thefirst drain/source terminal of the control transistor Tc1 to the firstdrain/source terminal of the antifuse transistor Taf through the controltransistor Tc1 and the control transistor Tc2. Consequently, the voltageat the gate terminal of the antifuse transistor Taf is higher than thevoltage at the first drain/source terminal of the antifuse transistorTaf. Under this circumstance, a voltage stress with the positivepolarity (+8V) is provided to the region across the gate oxide layer ofthe antifuse transistor Taf.

Since the voltage stress with the positive polarity (+8V) is largelybeyond the withstanding voltage of the antifuse transistor Taf, aprogram current Ip with the higher magnitude is generated. The programcurrent Ip flows along the pre-established weak path. Consequently, thegate oxide layer of the antifuse transistor Taf is ruptured. Moreover,the program current Ip flows in a second direction. That is, the programcurrent Ip flows from the gate terminal of the antifuse transistor Tafto the first drain/source terminal of the antifuse transistor Taf.

After the two stages of the program cycle are completed, the OTP memorycell is programmed to the first storing state. Moreover, it is confirmedthat the ruptured position of the gate oxide layer is arranged betweenthe gate terminal of the antifuse transistor Taf and the firstdrain/source terminal of the antifuse transistor Taf.

FIG. 8A is a schematic equivalent circuit diagram of an antifuse-typeone time programmable memory cell according to a further embodiment ofthe present invention. The OTP memory cell 80 comprises a controltransistor Tc and an antifuse transistor Taf. A first drain/sourceterminal of the antifuse transistor Taf and a second drain/sourceterminal of the antifuse transistor Taf are connected with each other.Consequently, the antifuse transistor Taf is formed as a MOS capacitor.A first drain/source terminal of the control transistor Tc is connectedwith a bit line BL. A gate terminal of the control transistor Tc isconnected with a word line WL. The first drain/source terminal of theantifuse transistor Taf is connected with a second drain/source terminalof the control transistor Tc. A gate terminal of the antifuse transistorTaf is connected with the antifuse control line AF.

FIG. 8B schematically illustrates associated voltage signals forprogramming the OTP memory cell FIG. 8A to the first storing state inthe first stage of the program cycle. In the first stage of the programcycle, a bit line voltage Vb1 is provided to the bit line BL, a controlvoltage Vdd is provided to the word line WL, and a program voltage Vp1is provided to the antifuse control line AF. In an embodiment, thecontrol voltage Vdd is 3V, the bit line voltage Vb1 is 2V, and theprogram voltage Vp1 is 0V. That is, the bit line voltage Vb1 is higherthan the program voltage Vp1.

Since the control transistor Tc is turned on, the bit line voltage Vb1(2V) is transmitted from the first drain/source terminal of the controltransistor Tc to the first drain/source terminal of the antifusetransistor Taf through the control transistor Tc. Under thiscircumstance, a voltage stress with the negative polarity (−2V) isprovided to the antifuse transistor Taf. In other words, under the abovebias condition of the first stage, there will be a localized oxidedamage region generated in the gate oxide layer of the antifuse Taf toform the weak path. In addition, a weak path is formed on the gate oxidelayer of the antifuse transistor Taf.

Since the first drain/source terminal of the antifuse transistor Taf andthe second drain/source terminal of the antifuse transistor Taf areconnected with each other, the weak path is formed between the gateterminal of the antifuse transistor Taf and the first drain/sourceterminal of the antifuse transistor Taf or between the gate terminal ofthe antifuse transistor Taf and the second drain/source terminal of theantifuse transistor Taf. In the embodiment of FIG. 8B, the weak path isformed between the gate terminal of the antifuse transistor Taf and thefirst drain/source terminal of the antifuse transistor Taf. In addition,a weak current iw in a first direction flows through the weak path. Theweak current iw flows from the first drain/source terminal of theantifuse transistor Taf to the gate terminal of the antifuse transistorTaf.

FIG. 8C schematically illustrates associated voltage signals forprogramming the OTP memory cell FIG. 8A to the first storing state inthe second stage of the program cycle. In the second stage of theprogram cycle, a bit line voltage Vb2 is provided to the bit line BL,the control voltage Vdd is provided to the word line WL, and a programvoltage Vp2 is provided to the antifuse control line AF. In anembodiment, the bit line voltage Vb2 is 0V, and the program voltage Vp2is 8V. That is, the program voltage Vp2 is higher than the bit linevoltage Vb1, and the bit line voltage Vb1 is higher than the bit linevoltage Vb2.

Since the control transistor Tc is turned on, the bit line voltage Vb2(e.g., 0V) is transmitted from the first drain/source terminal of thecontrol transistor Tc to the first drain/source terminal of the antifusetransistor Taf through the control transistor Tc1. Under thiscircumstance, a voltage stress with the positive polarity (+8V) isprovided to the antifuse transistor Taf. Moreover, a program current Ipis generated. The program current Ip flows along the pre-establishedweak path. Consequently, the gate oxide layer of the antifuse transistorTaf is ruptured. Moreover, the program current Ip flows in a seconddirection. That is, the program current Ip flows from the gate terminalof the antifuse transistor Taf to the first drain/source terminal of theantifuse transistor Taf.

After the two stages of the program cycle are completed, the OTP memorycell is programmed to the first storing state. Moreover, it is confirmedthat the ruptured position of the gate oxide layer is arranged betweenthe gate terminal of the antifuse transistor Taf and the firstdrain/source terminal of the antifuse transistor Taf.

FIG. 9 is a schematic circuit diagram illustrating a variant example ofthe OTP memory cell of FIG. 8A. In comparison with the OTP memory cellof FIG. 8A, the OTP memory cell 90 of this embodiment comprises aantifuse transistor Taf1 and a antifuse transistors Taf2. Since the OTPmemory cell 90 is equipped with the two antifuse transistors, thereliability of the OTP memory cell is enhanced. A first drain/sourceterminal of the first antifuse transistor Taf1 and a second drain/sourceterminal of the first antifuse transistor Taf1 are connected with eachother. A gate terminal of the first antifuse transistor Taf1 isconnected with an antifuse control line AF1. A first drain/sourceterminal of the second antifuse transistor Taf2 and a seconddrain/source terminal of the second antifuse transistor Taf2 areconnected with each other. A gate terminal of the second antifusetransistor Taf2 is connected with an antifuse control line AF2. The waysof programming the OTP memory cell 90 to the first storing state aresimilar to those of FIGS. 8B and 8C, and are not redundantly describedherein.

From the above descriptions, the OTP memory cell is programmed to thefirst storing state in two stages during the program cycle.Consequently, it is confirmed that the ruptured position of the gateoxide layer is arranged at the weak path. That is, the ruptured positionof the gate oxide layer is arranged between the gate terminal of theantifuse transistor Taf and the first drain/source terminal of theantifuse transistor Taf. Consequently, the possibility of misjudging thestoring states of OTP memory cells is largely reduced.

In the above embodiments, the method of programming the OTP memory cellto the second storing state is not described. Since the gate oxide layerof the antifuse transistor Taf in the second storing state is notruptured, the method of programming the OTP memory cell to the secondstoring state is similar to that of FIG. 2B. Since the controltransistor Tc is turned off, the voltage stress cannot be provided tothe gate oxide layer of the antifuse transistor Taf. Under thiscircumstance, the gate oxide layer of the antifuse transistor Taf is notruptured.

In the above embodiments, the transistors of the OTP memory cell areN-type transistors (e.g., NMOS transistors). It is noted that the typesof transistors used in the OTP memory cell are not restricted. In someother embodiment, the transistors of the OTP memory cell are P-typetransistors (e.g., PMOS transistors). Furthermore, It is noted that thevoltage signals for programming and reading the OTP memory cell are notrestricted. In some other embodiment, other voltage signals may use toprogram or read the OTP memory cell.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not be limited to the disclosedembodiment. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

What is claimed is:
 1. A method for programming an antifuse-type onetime programmable memory cell, the antifuse-type one time programmablememory cell comprising a first control transistor and a first antifusetransistor, the first control transistor comprising a gate terminal, afirst drain/source terminal and a second drain/source terminal, thefirst antifuse transistor comprising a gate terminal and a firstdrain/source terminal, the first drain/source terminal of the firstantifuse transistor being connected with the second drain/sourceterminal of the first control transistor, the method comprising stepsof: (a) providing a first program voltage to the gate terminal of thefirst antifuse transistor and turning on the first control transistor,wherein a first bit line voltage is transmitted from the firstdrain/source terminal of the first control transistor to the firstdrain/source terminal of the first antifuse transistor, a first voltagestress with a first polarity is provided to a gate oxide layer of thefirst antifuse transistor, and a weak path is formed between the gateterminal of the first antifuse transistor and the first drain/sourceterminal of the first antifuse transistor; and (b) providing a secondprogram voltage to the gate terminal of the first antifuse transistorand turning on the first control transistor, wherein a second bit linevoltage is transmitted from the first drain/source terminal of the firstcontrol transistor to the first drain/source terminal of the firstantifuse transistor, a second voltage stress with a second polarity isprovided to the gate oxide layer of the first antifuse transistor, and aprogram current is generated along the weak path, so that the gate oxidelayer of the first antifuse transistor is ruptured.
 2. The method asclaimed in claim 1, wherein a first control voltage is provided to thegate terminal of the first control transistor, so that the first controltransistor is turned on.
 3. The method as claimed in claim 1, whereinthe first control transistor and the first antifuse transistor areN-type transistors, wherein the first bit line voltage is higher thanthe first program voltage, the second program voltage is higher than thefirst bit line voltage, and the first bit line voltage is higher thanthe second bit line voltage.
 4. The method as claimed in claim 3,wherein in the step (a), a weak current in a first direction is furthergenerated, and the weak current flows along the weak path and flows fromthe first drain/source terminal of the first antifuse transistor to thegate terminal of the first antifuse transistor.
 5. The method as claimedin claim 4, wherein in the step (b), the program current flows in asecond direction along the weak path, and flows from the gate terminalof the first antifuse transistor to the first drain/source terminal ofthe first antifuse transistor.
 6. The method as claimed in claim 1,wherein the first drain/source terminal of the first control transistoris connected with a bit line, the gate terminal of the first controltransistor is connected with a word line, and the gate terminal of thefirst antifuse transistor is connected with a first antifuse controlline.
 7. The method as claimed in claim 1, wherein the antifuse-type onetime programmable memory cell comprises: a second control transistor,wherein a first drain/source terminal of the second control transistoris connected with a bit line, and a gate terminal of the second controltransistor is connected with a word line; the first control transistor,wherein the gate terminal of the first control transistor is connectedwith a select line, and the first drain/source terminal of the firstcontrol transistor is connected with a second drain/source terminal ofthe second control transistor; and the first antifuse transistor,wherein the gate terminal of the first antifuse transistor is connectedwith a first antifuse control line, and the first drain/source terminalof the first antifuse transistor is connected with the seconddrain/source terminal of the first control transistor.
 8. The method asclaimed in claim 1, wherein the first drain/source terminal of the firstcontrol transistor is connected with a bit line, the gate terminal ofthe first control transistor is connected with a word line, the gateterminal of the first antifuse transistor is connected with a firstantifuse control line, and the first drain/source terminal of the firstantifuse transistor and a second drain/source terminal of the firstantifuse transistor are connected with each other.
 9. The method asclaimed in claim 8, wherein the antifuse-type one time programmablememory cell comprises: the first control transistor; the first antifusetransistor; and a second antifuse transistor, wherein a gate terminal ofthe second antifuse transistor is connected with a second antifusecontrol line, a first drain/source terminal of the second antifusetransistor is connected with the second drain/source terminal of thefirst control transistor, and the first drain/source terminal of thesecond antifuse transistor and a second drain/source terminal of thesecond antifuse transistor are connected with each other.